Trenched mosfets with part of the device formed on a (110) crystal plane

ABSTRACT

This invention discloses an improved MOSFET devices manufactured with a trenched gate by forming the sidewalls of the trench on a (110) crystal orientation of a semiconductor substrate. The trench is covering with a dielectric oxide layer along the sidewalls and the bottom surface or the termination of the trench formed along different crystal orientations of the semiconductor substrate. Special manufacturing processes such as oxide annealing process, special mask or SOG processes are implemented to overcome the limitations of the non-uniform dielectric layer growth.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates generally to the semiconductor power devices. Moreparticularly, this invention relates to a novel and improved manufacturemethod and device configuration for a P-channel metal-oxidesemiconductor field effect transistor (MOSFET) trenched power devicemanufactured with channel oriented on a (110) crystal plane of a siliconwafer.

2. Description of the Prior Art

Even thought the techniques to provide improved carrier mobility for aP-channel MOSFET, i.e., metal oxide silicon field effect transistors, byforming the transistor on a (110) crystal plane is known, thedifficulties of high interface state density is still a limitation forpractical implementation of such configurations. Specifically, Szedisclosed in “Physics of Semiconductor Devices” (Wiley-Interscience,1969, pp. 16, pp. 473) and B. Goebel, D. Schumann, E. Bertagnollidisclosed in IEEE Trans. Electronics Devices, Vol. 48, No. 5, May 2001,pp. 897-906 that there is a thicker oxidation and higher interface statedensity along a (110) crystal plane. The thicker oxidation thus resultsin a thick gate oxide layer and lead to an adversely affected higherthreshold voltage.

Historically, the MOS devices are formed on the silicon wafer along acrystal orientation of a (100) plane because the oxide layer grown on a(100) plane has the lowest fixed charge and interface state density. Forthese reasons, the trench walls of the N-channel and P-channel of thetrenched MOSFETs are typically oriented along the (100) plane as well.Specifically, for a N-channel device, the channel formed along the (100)orientation has the benefit for achieving higher channel mobility. Incontrast, the oxide layer grown along the (110) plane has greaterthickness and higher interface state density. A thicker oxide layeroften leads to a higher threshold voltage and lower transconductance.Furthermore, measured data also provide some evidence that thicker oxidelayer also causes a degradation of channel mobility. Due to theseconcerns, forming the MOSFET power devices using a (100) crystalorientation has become a common rule in the conventional design methods.However, there are potential benefits of forming the power MOSFETdevices or at least part of the transistors on the (110) plane. Thesepotential benefits are often ignored due to the common practice astypically carried out by those of ordinary skill in the art withoutfurther exploration. Furthermore, even when there are several US patentsand patent applications that explored the techniques of building the MOSdevices on a semiconductor substrate having a (110) crystal orientation,these disclosures are still limited by several technique difficultiesdue to different practical configuration and manufacture constraints dueto the oxide layer thickness variations along different crystalorientations as will be discussed below.

In U.S. Pat. No. 4,933,298, entitled “Method of making high speedsemiconductor device having a silicon-on-insulator structure”, Hasegawadiscloses a CMOS silicon-on-insulation structure fabricated by firstforming an insulating SiO2 layer on a silicon substrate having a (110)plane. Openings are then formed in the SiO2 layer to expose a part ofthe substrate, and a polycrystalline or an amorphous silicon layer isdeposited on the SiO2 layer and in the openings. The deposited siliconlayer is divided into islands so that a first island includes one of theopenings and a second island does not include any openings. A laser beamis then irradiated onto the islands so as to melt the islands, and whenthe laser light irradiation is discontinued, the melted islandsrecrystallize so that the first island forms a (110) plane and thesecond island forms a (100) plane. A p-channel MOSFET is fabricated onthe first island, and an re-channel MOSFET is fabricated on the secondisland. The thus paired CMOS operates at high speeds, because thep-channel MOSFET using positive holes as the carrier is fast in a (110)crystal, and the n-channel MOSFET using electrons as the carrier is fastin a (100) crystal. Hasegawa disclose the benefits of building ap-channel MOSFET in a (110) crystal plane, however the configurationsand method as disclosed would be too complicate and costly with limitedmerits for practical application to build a commercial MOSFET product.

In another U.S. Pat. No. 6,245,615 entitled “Method and apparatus on(110) surfaces of silicon structures with conduction in the (110)direction” Noble et al. disclosed methods and structures that arelateral to surfaces with a (110) crystal plane orientation such that anelectrical current of such structures is conducted in the (110)direction for the purposed of achieving improvements in hole carriermobility. The structure's channel is oriented in a (110) plane such thatthe electrical current flow is in the (110) direction. A method offorming an integrated circuit includes forming a trench in a siliconwafer with the trench wall oriented to have a (110) crystal planeorientation. A semiconductor device is also formed lateral to the trenchwall such that the semiconductor device is capable of conducting anelectrical current in a (110) direction. The method disclosed by Nobleet al. provides for forming an integrated circuit including an array ofMOSFETs and another method includes forming an integrated circuitincluding a number of lateral transistors. The disclosure also includesstructures as well as systems incorporating such structures all formedaccording to the methods provided in this application. Noble'sdisclosures are however for a lateral device. A vertical trench MOSdevice would require different considerations.

FIG. 1 shows a typical trench power MOSFET device that has its MOSchannel vertically along the sidewall of a trench 10. The trenchsidewall is covered by the gate dielectric 20, and is filled with thegate electrode material 30. Current flows from the source contact 40 tothe drain contact 50, vertically down along the channel when the gatevoltage is sufficient to connect the source and drain regions by aninversion layer of mobile carriers, e.g., electrons for n-channel andholes for p-channel. Many such cells operated in parallel form a powerMOSFET.

Table 1 shows the measured data that summarizes the characteristics oftwo identical MOSFETs next to each other on the same wafer, with thechannel formed on (100) and (110) interfaces respectively on a (100)wafer. An (110) orientation is achieved by simply rotating the FETs by45 degrees as can be seen from FIG. 2. The results from two MOSFETs withchannel formed on (100) and (110) orientations are shown. The onlydifference in process between the two MOSFETs with channel formed on(100) and (110) orientations is the duration of gate oxidation.

Estimated Rds1 Rds2 Rds3 Crystal Oxide Vgs = Vgs = Vgs = Orientationthickness Vth 10 V 4.5 V 2.5 V Qg 100 250 0.99 0.37 0.37 0.37 1.02 Å VOhm Ohm Ohm nC 110 330 1.33 0.31 0.31 0.31 0.82 Å V Ohm Ohm Ohm nCEstimated Rds1 Rds2 Crystal Oxide Vgs = Vgs = Orientation thickness Vth10 V 4.5 V Qg 100 450 1.7 0.37 0.83 Å V Ohm Ohm 110 600 2.6 0.31 0.78 ÅV Ohm Ohm

It is clear from those measured data that there is a significantincrease in threshold voltage, i.e., Vth, caused by the thicker oxidefor (110) oriented device. However, there is a marked improvement inon-resistance, especially at higher gate bias, showing that there mustbe a large improvement in the hole-channel mobility.

Therefore, a need still exists in the art of MOSFET device design andmanufacture to provide new design method and device configuration informing the MOSFET channel along the (110) plane to achieve deviceperformances.

SUMMARY OF THE PRESENT INVENTION

It is therefore an object of the present invention to provide a newdesign and manufacturing methods and device configuration for the powerMOSFET devices to take advantages of building the devices on planes ofdifferent crystal orientations such that the limitations of theconventional methods can be overcome.

Specifically, it is an object of the present invention to provideimproved MOSFET devices manufactured with a trenched gate by forming thesidewalls of the trench on a (110) crystal orientation of asemiconductor substrate. The trench is covering with a dielectric oxidelayer along the sidewalls and the bottom surface or the termination ofthe trench formed along different crystal orientations of thesemiconductor substrate. Special manufacturing processes such as oxideannealing process, special mask or SOG processes are implemented toovercome the limitations of the non-uniform dielectric layer growth. Ina special preferred embodiment, forming the trenches with a stripeconfiguration, and choosing a different orientation of the seed crystalcan produce an orientation of the trench with all sidewalls and bottomsurface align along a (110) crystal orientation of the semiconductorsubstrate.

Briefly in a preferred embodiment this invention discloses a trenchedMOSFET power transistor that includes a gate disposed in a trench formedin a semiconductor substrate. The trench further includes sidewalls anda trench bottom surface all formed along a (110) crystal orientation ofthe semiconductor substrate. In a preferred embodiment, the MOSFET powertransistor is a P-channel MOSFET power transistor. In another preferredembodiment, the MOSFET power transistor is a N-channel MOSFET powertransistor. In a different preferred embodiment, this invention furtherdiscloses a trenched MOSFET power transistor comprising a gate disposedin a trench formed in a semiconductor substrate. The trench furtherincludes sidewalls formed along a first crystal orientation of thesemiconductor substrate and a trench bottom surface formed along asecond crystal orientation of the semiconductor substrate different fromthe first crystal orientation. The trench further includes an oxidelayer covering the sidewalls having a substantially a same thickness asan oxide layer covering the bottom surface of the trench.

These and other objects and advantages of the present invention will nodoubt become obvious to those of ordinary skill in the art after havingread the following detailed description of the preferred embodiment,which is illustrated in the various drawing figures.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross sectional view of a MOSFET device manufacturedaccording to a conventional manufacturing process;

FIG. 2 shows two trenches opened for two identical MOSFETs next to eachother on the same wafer, with the channel formed on (100) and (110)interfaces respectively on a (100) wafer.

FIGS. 3A and 3B are perspective views for showing the crystalorientations of a silicon ingot and the configuration of a trench;

FIG. 4A to 4C are cross sectional views for showing the process to formthe trench aligned along different crystal orientations of asemiconductor substrate;

FIG. 5 is a perspective view for showing the termination tip of a trenchto minimize the (100) plane effect;

FIGS. 6A to 6C are perspective views for showing manufacturing processesusing SOG to thicken the oxide at the termination of a trench;

FIGS. 7A and 7B are perspective views for showing an annealing processto produce trench oxide layer covering (110) and (100) planes of uniformthickness;

FIGS. 8A to 8C show the cross sectional view of another embodiment using(100) wafer as starting material, following the steps described in FIGS.4A-4C;

FIG. 9 is a perspective view of a P-channel DMOS with channel and trenchbottom both along (110) plane; and

FIG. 10 is a perspective view of a wafer and the trench for a N-channeltrenched MOSFET device with the bottom of the trench formed on a (110)plane and the sidewalls on the (100) plane.

DETAILED DESCRIPTION OF THE METHOD

For P-channel implementations, FIGS. 3A and 3B show the orientations ofthe substrate and trench according to the current invention. In FIG. 3A,the silicon ingot 125 is grown in the (110) plane. The silicon ingot 125provides a configuration that four sidewalls are situated with foursidewall surfaces forming a corner with a corner angle of 90 degrees,thus these sidewall surfaces are perpendicular to each other. Two ofthese sidewalls are along a (100) crystal orientation and two are alonga (110) crystal orientation. Referring to FIG. 3A, two sidewalls 150 andbottom 155 of the trench 148 are formed along a (110) crystalorientation while the termination end surface 160 of the trench 148 isformed along a (100) crystal orientation. In FIG. 3B, the wafer 325 isformed by rotating a normal (100) wafer as shown in FIG. 2 by 45

thus forming two interface planes on a (110) plane while the top andbottom planes are still on the (100) plane. As can be observed from FIG.3B, when a trench 348 is formed with the sidewalls 350 along the (110)plane, the bottom 355 of the trench is still oriented along a (100)plane. Due to these different orientations, the gate oxide layer alongthe sidewalls formed along the (110) will be thicker than the gate oxidelayer formed on the bottom of the trench along the (100) plane duringthermal oxidation process. In order to fabricate a device capable of anoperating voltage at a given gate voltage, the thin oxide bottom or endsurface of the trench sets the minimum oxide thickness usable. This thenforces the use of a thicker oxide along the sidewall compared to adevice with all trench sides along the (100), and causes a higherthreshold voltage for a given channel doping profile. To minimize theeffect of (100) surface, stripe structure design with round terminationor round bottom is incorporated with dielectric layer thickeningtechniques to provide improve P-channel trench MOSFET device.

Referring to FIG. 4A, one embodiment uses (110) wafer 125 as substrate.An oxide layer 135 is formed on the top (110) surface by thermaloxidation. A trench mask 145 is used to expose the silicon dioxide inthe area for forming the trenches as shown in FIG. 4C below. In oneembodiment, the trench mask may have a round or oval shape where thetrench ends. As shown in FIG. 5, this produces a trench with roundtermination therefore the section lying along the (100) plane duringtrench dry etching process is minimized. Referring to FIG. 4B, after theexposed oxide is removed by etching, the photoresist 145 is stripped offand the remaining oxide layer 135 forms the hard mask for forming thetrenches where the oxide layer 135 is removed. Referring now to FIG. 4C,the trenches 148 are then formed along the (110) direction on the waferby dry etching process. Thus, by using a stripe design, it is possiblefor the trench MOSFET to have the trench sidewalls 150 and the channel,and the trench bottom 155 along a (110) interface, making the gate oxidethickness uniform both along the sidewall and at the trench bottom.Therefore, the on resistance of the device may be reduced. However, asthat shown in FIG. 5, in the area 160 where the trench terminates, somepart of the tip will be in the (100) plane. The gate oxide may bethinner at the trench termination area 160 thus limiting gate maximumrating of the gate oxide.

In order to overcome the technical difficulties caused by a non-uniformthickness of the gate dielectric layer when part of the device is formedalong different crystal orientations, the thickness of oxide layeraround (100) plane is enhanced to provide a gate oxide layer withuniform thickness or even thicker at the trench bottom or at the trenchtermination. Numerals oxide thickening techniques may be used to achievethe above design goal. Several measures are disclosed in this invention.

FIGS. 6A to 6C shows another P-channel MOSFET device 200 that has aconfiguration with the trench sidewalls formed along the (110) planewhile using a mask to form thicker oxide in the designated areas thusminimizing the effects of uneven thickness of gate oxide layer. Afterthe trench is formed, it is filled with oxide 210 using techniques suchas SOG (spin on glass) or oxide deposition as shown in FIG. 6A.Alternatively, an oxide layer may thermally be grown over the entireSilicon surface. A mask 220 is used to generate a protection area at thetrench termination as that shown in FIG. 6B. The oxide is then etchedback with the oxide in the terminal area intact as that shown in FIG.6C. A sacrificial oxide layer may be thermally grown and then removed bywet etch to remove the defects on silicon surface on the bottom and thesides of the trench caused by the harsh etching process during trenchformation and SOG etch back. A high quality gate oxide is then thermallygrown (not shown).

FIGS. 7A to 7B show another embodiment, using a high temperature gateanneal to flow the oxide, so its thickness loses its orientationdependence. As seen in FIG. 7A, when following the regular process, thegate oxide layer 260 is thinner at the trench termination tip portion of(100) plan. After annealing at a temperature higher than 950

C, silicon oxide goes into viscous flow and losses its orientationdependence to yield a film with uniform thickness. FIG. 7B shows theresult after 1200

C of annealing for 5 minutes.

FIGS. 8A to 8C show another embodiment using (100) wafer 325 as startingmaterial. Following the steps described in FIGS. 4A-4C, a trench 348with both side walls 350 and termination end faces (not shown) on (110)plane is obtained. The trench bottom 355 is in (100) plane. Anadditional ion reactive etching process is performed to round the bottom355 of the trench. To overcome the technical difficulties caused by anon-uniform thickness of the gate oxide layer when part of the device isformed along different crystal orientations, the thickness of oxidelayer around (100) trench bottom is enhanced to provide a gate oxidelayer with uniform thickness or even thicker at the trench bottom or atthe trench termination. Referring to FIG. 8B, a layer of oxide isdeposited to fill the bottom of trench. Alternatively, polysilicon maybe deposited and then oxidized, or SOG may be used to fill the trench.The oxide is then etched back. In one embodiment, the oxide is etchedwith a mask. In another embodiment, the oxide is etched backed withoutusing a mask. The etch back process goes on until the thickness of thebottom oxide 310 reaches a predetermined thickness (FIG. 8C). Asacrificial oxide layer may be thermally grown and then removed by wetetch to remove the defects on silicon surface on the sides of the trenchcaused by the harsh etching process during trench formation and oxideetch back. A high quality gate oxide is then thermally grown. As shownin FIG. 8D, this yields a layer of gate oxide 320 lining within thetrench 348 where the oxide thickness at the bottom portion 355 has beenincreased so that the over all thickness is substantially the same.

Other techniques and any of combinations of these techniques includingthose mentioned above can be used to increase the thickness of thindielectric layer portion in the trench when part of the device is formedalong different crystal orientations. will improve the device ratingwithout deteriorate the performance.

After the gate dielectric layer is formed in the trench, standard trenchMOSFET processes are carried out to complete the fabrication of a MOSFETdevice 400 as that shown in FIG. 9. The processes for the formation ofthe gate 410, the body 420, the source 430, BPSG deposition 440, andcontact with the substrate 405 functioning as a drain are well know inthe art, to form the device as shown in FIG. 9. This invention disclosesa trenched MOSFET device 400 formed on a silicon substrate withsidewalls of the trench formed along a (110) crystal plane. Thesidewalls and the bottom surface are covered with an dielectric layer415 having substantially a uniform thickness on the sidewalls and thebottom surface. In one embodiment, the trench and gate is formed beforethe formation of body or source. In another embodiment, the trench andgate is formed after the formation of body or source.

Referring to FIG. 10 are perspective views for forming an N-channeltrenched MOSFET device with a part of the device on a (110) plane. Thewafer 510 is a (110) wafer. A stripe design is implemented wherein atrenched N-channel MOSFET 500 is formed with the trenches 520perpendicular to the (110) direction. This orientation of the trenchresults in a configuration where the sidewalls 525 of the trench 520 areformed on the (100) plane while the bottom of the trench 530 is formedon a (110) plane. This process naturally produces a thicker gate oxideon the bottom of the trench. The thicker oxide at the bottom has severaladvantages that the thick gate oxide at the bottom reduces thegate-drain capacitance, leading to a faster switching MOSFET.Furthermore, the thicker gate oxide at the bottom of the trench reducesthe electric field at the trench bottom, increasing the breakdownvoltage. This allows the designer to increase the epitaxial layerdoping, thereby lowering the on-resistance of the MOSFET. For a stripeconfiguration as shown, the trench termination will also lie on a 110plane, and since the oxide is thicker here, there is no penalty in gatevoltage rating.

Thus this invention discloses a N-channel MOSFET device having a trenchwherein a sidewall of the trench is oriented along a different crystalorientation than a bottom of the sidewall. In a preferred embodiment,the bottom of the trench is oriented along a (110) crystal plane. Inanother preferred embodiment, the sidewall is oriented along a (100)crystal plane. In yet another embodiment, the trench and gate is formedbefore the formation of body or source. In yet another embodiment, thetrench and gate is formed after the formation of body or source.

Although the present invention has been described in terms of thepresently preferred embodiment, it is to be understood that suchdisclosure is not to be interpreted as limiting. Various alterations andmodifications will no doubt become apparent to those skilled in the artafter reading the above disclosure. Accordingly, it is intended that theappended claims be interpreted as covering all alterations andmodifications as fall within the true spirit and scope of the invention.

1. A trenched semiconductor power device comprising a gate disposed in atrench formed in a semiconductor substrate wherein: said trench furthercomprising sidewalls formed along a first crystal orientation of saidsemiconductor substrate for enhancing a carrier mobility in a channelalong said first crystal orientation disposed near said sidewalls in anactive cell region of said substrate and said trench further comprisinga trench bottom surface formed along a second crystal orientationdifferent from said first crystal orientation of said semiconductorsubstrate and said trench further comprising a single thermally growngate oxide layer covering said sidewalls and simultaneously coveringsaid bottom surface having a substantially same gate oxide thickness. 2.The trenched semiconductor power device of claim 1 wherein: saidsemiconductor power device is a P-channel MOSFET power device and saidsidewalls formed along a (110) crystal orientation of said semiconductorsubstrate for enhancing a P-type carrier mobility along a P-channelalong said (110) crystal orientation whereby said P-channel MOSFET powerdevice having a reduced on-resistance.
 3. The trenched semiconductorpower device of claim 1 wherein: said sidewalls of said trench formedalong a (110) crystal orientation and said bottom surface of said trenchhaving a round-shaped surface with an enhanced thermal oxide growth rateand formed along a (100) crystal orientation of said semiconductorsubstrate wherein said round-shaped bottom surface is covered with athermally grown single gate oxide layer substantially of same thicknessas a gate oxide layer covering said sidewalls.
 4. The trenchedsemiconductor power device of claim 2 wherein: said sidewalls and saidbottom surface of said trench are covered with an annealed single gateoxide layer having substantially a same gate oxide layer thickness.
 5. Atrenched MOSFET power transistor comprising a gate disposed in a trenchformed in a semiconductor substrate wherein: said trench furthercomprising sidewalls formed along a first crystal orientation of saidsemiconductor substrate for enhancing a carrier mobility in a channeldisposed near said sidewalls in an active cell region of said substratealong said first crystal orientation and a trench bottom surface formedalong a second crystal orientation of said semiconductor substratedifferent from said first crystal orientation; and said trench furthercomprising a single dielectric layer having different thicknessformation rates on said sidewalls and said trench bottom covering saidsidewalls having a substantially a same thickness as a simultaneouslyformed single dielectric layer covering said bottom surface of saidtrench.
 6. The trenched MOSFET power transistor of claim 5 wherein: saidsidewalls are formed along a (110) crystal orientation and said bottomsurface is formed along a (100) crystal orientation wherein said singledielectric layer having a higher thickness formation rate on saidsidewalls than said simultaneously formed single dielectric layer onsaid bottom surface.
 7. The trenched MOSFET power transistor of claim 5wherein: said MOSFET power transistor is a P-channel MOSFET powertransistor and said sidewalls are formed along a (110) crystalorientation with an enhanced P-carrier mobility along said (110) crystalorientation and said bottom surface is formed along a (100) crystalorientation.
 8. The trenched MOSFET power transistor of claim 5 wherein:at least one of sidewalls is formed along a (100) crystal orientationhaving a round sidewall surface to improve a dielectric thicknessformation rate thereon and said bottom surface is formed along a (110)crystal orientation wherein said dielectric layer having a lowerthickness formation rate on a surface along a (100) crystal orientationthan a thickness formation rate on a (110) crystal orientation.
 9. AnN-channel trenched MOSFET power transistor includes a trenched gatedisposed in a trench wherein: sidewalls of said trench are formed alonga (100) crystal orientation and a trench bottom surface is formed alonga (110) crystal orientation both covered by a single thermally growndielectric layer wherein said dielectric layer on said bottom surface isslightly thicker than said dielectric layer on said sidewall surface forreducing a gate-to-drain capacitance.
 10. The trenched MOSFET powertransistor of claim 5 wherein: said single thermally grown dielectriclayer is an oxide layer having substantially a same thickness coveringsaid sidewalls and said bottom surface of said trench wherein saidsingle thermally grown oxide layer having a higher thickness formationrate on said sidewalls than on said bottom surface.
 11. A trenchedMOSFET power transistor comprising a gate disposed in a trench formed ina semiconductor substrate wherein: said trench disposed in an activecell area further comprising two sidewalls formed along a first crystalorientation with an enhanced carrier mobility along said first crystalorientation and two other sidewalls formed along a second crystalorientation of said semiconductor substrate and a trench bottom surfaceformed along said second crystal orientation different from said firstcrystal orientation of said semiconductor substrate; and said trenchfurther comprising a single dielectric layer covering said sidewallshaving a substantially same thickness as a simultaneously formed singledielectric layer covering said bottom surface of said trench.
 12. Thetrenched MOSFET power transistor of claim 11 wherein: said MOSFET powertransistor is a P-channel MOSFET power transistor having an enhancedP-type carrier mobility along a channel formed near said sidewalls of(110) crystal orientation whereby said P-channel MOSFET power transistorhaving a reduced on-resistance.
 13. The trenched MOSFET power transistorof claim 11 wherein: said dielectric layer is a single thermally grownoxide layer having substantially a same thickness covering saidsidewalls and said bottom surface of said trench wherein two of saidsidewalls formed along said second crystal orientation having a roundsidewall surface for improving a formation rate of said single thermallygrown oxide layer thereon in order to form said single thermally grownoxide layer to have said substantially a same thickness covering saidtwo sidewalls formed along said first crystal orientation.
 14. Atrenched MOSFET power transistor comprising a gate disposed in a trenchformed in an active cell area of a semiconductor substrate wherein: saidtrench constituting an elongated stripe further comprising sidewallsalong an elongated direction formed along a first crystal orientation ofsaid semiconductor substrate for improving a device performance of saidMOSFET power transistor with an enhanced carrier mobility along saidfirst crystal orientation and a trench termination end surface atterminal ends of said elongated stripe along a second crystalorientation of said semiconductor substrate different from said firstcrystal orientation wherein said termination having a end surface havinga different surface shape for providing a different dielectric layerformation rate thereon.
 15. The trenched MOSFET power transistor ofclaim 14 wherein said termination end surface having a curved surfacewith said enhanced dielectric layer formation rate along said secondcrystal orientation of said semiconductor substrate whereby deviceperformance improvements along said sidewalls formed in said firstcrystal orientation along said elongated direction may be increased anddevice performance differences arising from said second crystalorientation on said termination end surface are reduced.
 16. Thetrenched MOSFET power transistor of claim 14 wherein: said sidewall areformed along a (110) crystal orientation and said termination endsurface is formed along a (100) crystal orientation.
 17. The trenchedMOSFET power transistor of claim 14 wherein: said MOSFET powertransistor is a P-channel MOSFET power transistor and said sidewallsformed along a (110) crystal orientation of said semiconductor substratefor enhancing a P-type carrier mobility along a channel aligned in said(110) crystal orientation whereby said P-channel MOSFET power devicehaving a reduced on-resistance.
 18. The trenched MOSFET power transistorof claim 14 wherein: said MOSFET power transistor is a N-channel MOSFETpower transistor and said sidewalls along said elongated direction areformed along a (100) crystal orientation and said termination endsurface is formed along a (110) crystal orientation with an surfacehaving a surface shape for forming a end-surface dielectric layer havingsubstantially a same thickness as a dielectric layer formed on saidsidewalls.
 19. The trenched MOSFET power transistor of claim 14 wherein:said MOSFET power transistor is a N-channel MOSFET power transistor andsaid trench having a bottom surface formed along a (110) crystalorientation to form a single thermally grown oxide layer thereon havinga greater thickness than a single thermally grown oxide layer on saidsidewalls to reduce a gate-to-drain capacitance.
 20. A trenched MOSFETpower transistor comprising a gate disposed in a trench formed in anactive cell area of a semiconductor substrate wherein: said trenchconstituting an elongated stripe further comprising sidewalls along anelongated direction of said elongated stripe formed along a firstcrystal orientation of said semiconductor substrate for improving adevice performance of said MOSFET power transistor and a trenchtermination end surface at terminal ends of said elongated stripe havinga significantly less areas than said sidewalls along said elongateddirection formed along a second crystal orientation of saidsemiconductor substrate different from said first crystal orientation;and said trench further comprising an dielectric layer covering saidsidewalls and said termination end surface wherein said dielectric layerhaving different formation growth rates along said first crystalorientation and said second crystal orientation wherein said end surfacehaving significant less areas for reducing effects caused by saiddifferent formation growth rate along said second crystal orientation.21. The trenched MOSFET power transistor of claim 20 wherein: saidsidewall are formed along a (110) crystal orientation and saidtermination end surface is formed along a (100) crystal orientation forincreasing a device performance improvement because of sidewalls formedalong said (110) crystal orientation and a single thermally growndielectric layer having a substantially same thickness on said sidewallsand said termination end surface whereby device performance differencesarising from said end surface formed along said (100) crystalorientation may are reduced.
 22. The trenched MOSFET power transistor ofclaim 20 wherein: said MOSFET power transistor is a P-channel MOSFETpower transistor and said sidewalls formed along a (110) crystalorientation of said semiconductor substrate for enhancing a P-typecarrier mobility whereby said P-channel MOSFET power device having areduced on-resistance; and said trench constituting said elongatedstripe further comprising a trench bottom formed along a (100) trenchbottom surface covered by a single thermally grow oxide layer havingsubstantially a same thickness as an oxide layer covering saidsidewalls.
 23. The trenched MOSFET power transistor of claim 20 wherein:said MOSFET power transistor is a N-channel MOSFET power transistor andsaid sidewall along said elongated direction are formed along a (100)crystal orientation and said termination end surface is formed with acurve end surface to form a thicker dielectric layer thereon along a(110) crystal.
 24. The trenched MOSFET power transistor of claim 20wherein: said MOSFET power transistor is a N-channel MOSFET powertransistor and said trench having a bottom surface formed along a (110)crystal orientation to form a thicker oxide layer thereon than an singlethermally grown oxide layer covering said sidewalls to reduce agate-to-drain capacitance.
 25. The trenched MOSFET power transistor ofclaim 20 wherein: said dielectric layer is a single thermally grownoxide layer having a substantially a same thickness covering saidsidewalls and said termination end surface of said trench whereintermination end surface formed along said second crystal orientationhaving a round sidewall surface in order to form a single thermallygrown oxide layer to have said substantially a same thickness coveringsaid termination end surface formed along said first crystalorientation.
 26. A method for manufacturing a trenched MOSFET powertransistor by forming a trench in a semiconductor substrate and thenforming a gate in said trench wherein: said step of forming said trenchfurther comprising a step of forming said trench with sidewalls along afirst crystal orientation of said semiconductor substrate for enhancinga carrier mobility in a channel disposed near said sidewalls in anactive cell region of said substrate and forming a trench bottom surfacealong a second crystal orientation different from said first crystalorientation of said semiconductor substrate; and forming a singlethermally grown gate oxide layer covering said sidewalls and said bottomsurface of said trench having a substantially same gate oxide thickness.27. The method of claim 26 further comprising a step of: manufacturingsaid MOSFET power transistor as a P-channel MOSFET power transistor withsaid sidewalls surface along a (110) crystal orientation of saidsemiconductor substrate for enhancing a P-type carrier mobility wherebysaid P-channel MOSFET power device a reduced on-resistance wherein saidbottom surface of said trench is covering with said single thermallygrown oxide layer substantially of a same thickness as said singlethermally grown oxide layer on said sidewalls whereby a deviceperformance of said MOSFET is not adversely affected.
 28. A method formanufacturing a trenched MOSFET power transistor by forming a trench ina semiconductor substrate and then forming a gate in said trenchwherein: said step of forming said trench further comprising a step offorming said trench with sidewalls along a first crystal orientation ofsaid semiconductor substrate for enhancing a carrier mobility in achannel disposed near said sidewalls in an active cell region of saidsubstrate and a trench bottom surface along a second crystal orientationof said semiconductor substrate different from said first crystalorientation; and covering said sidewalls and said bottom surface with asingle thermally grown dielectric layer having different formation rateson said side wall and said trench bottom having substantially a samethickness on said sidewalls and said bottom surface.
 29. The method ofclaim 28 further comprising a step of: forming at least one of saidsidewall along a (110) crystal orientation and said bottom surface alonga (100) crystal orientation having a round bottom surface wherein saiddielectric layer having a lower thickness formation rate on said bottomsurface than said sidewall surface wherein said round bottom surfaceproviding an enhanced geometry to form said dielectric layer having saidsubstantially thickness on said bottom surface as said dielectric layeron said sidewalls.
 30. The method of claim 28 further comprising a stepof: manufacturing said MOSFET power transistor as a P-channel MOSFETpower transistor and forming said sidewalls surface along a (110)crystal orientation and said round bottom surface along a (100) crystalorientation.
 31. The method of claim 28 further comprising a step of:forming at least one of said sidewalls along a (100) crystal orientationhaving a round sidewall surface and said bottom surface along a (110)crystal orientation with said dielectric layer having a lower thicknessformation rate on said sidewalls than on said bottom surface whereinsaid round sidewall surface providing an enhanced geometry to form saiddielectric layer having said substantially thickness on said sidewallsurface as said dielectric layer on said bottom surface.
 32. A methodfor manufacturing an N-channel MOSFET power device having a trenchcomprising: forming sidewalls of said trench along a (100) crystalorientation and a trench bottom surface along a (110) crystalorientation and thermally growing a single oxide layer on said sidewallsand said trench bottom surface wherein said trench bottom surface havinga thicker layer of said single oxide layer covering said trench bottomsurface for reducing a gate-to-drain capacitance.
 33. A method formanufacturing a trenched MOSFET power transistor by forming a trench inan active cell area of a semiconductor substrate and then forming a gatein said trench wherein: said step of forming said trench furthercomprising a step of forming said trench as an elongated stripe withsidewalls along an elongated direction along a first crystal orientationof said semiconductor substrate for improving a device performance ofsaid MOSFET power transistor and a trench termination end surface atterminal ends of said elongated stripe having a curved surface wherebysaid termination end surface only having a small tip portion formedalong a second crystal orientation of said semiconductor substratedifferent from said first crystal orientation for improving a deviceperformance along said sidewalls formed in said first crystalorientation and reducing device performance differences arising fromsaid second crystal orientation on said small tip portion.
 34. Themethod of claim 33 further comprising a step of: forming said sidewallalong a (110) crystal orientation and said termination end surface alonga (100) crystal orientation for increasing a device performanceimprovement because of sidewalls formed along said (110) crystalorientation having significantly greater area than area of said endsurface and also for reducing device performance differences arisingfrom said end surface formed along said (100) crystal orientation. 35.The method of claim 33 further comprising a step of: manufacturing saidMOSFET power transistor as a P-channel MOSFET power transistor andforming said sidewalls along a (110) crystal orientation of saidsemiconductor substrate with said substantially greater area than saidarea of said end surface for enhancing a P-type carrier mobility wherebysaid P-channel MOSFET power device having a reduced on-resistance. 36.The method of claim 33 further comprising a step of: forming said MOSFETpower device as an N-channel device and forming said sidewall along saidelongated direction along a (100) crystal orientation and saidtermination end surface along a (110) crystal orientation having asubstantially smaller area than said sidewalls.
 37. The method of claim33 further comprising a step of: manufacturing said MOSFET powertransistor as a N-channel MOSFET power transistor by forming saidsidewall along said elongated direction along a (100) crystalorientation and forming said trench bottom surface along a (110) crystalorientation for increasing a oxide layer thickness thereon to reduce agate-to-drain capacitance.
 38. A method for manufacturing a trenchedMOSFET power transistor by forming a trench in an active cell area of asemiconductor substrate and then forming a gate in said trench wherein:said step of forming said trench further comprising a step of formingsaid trench as an elongated stripe with sidewalls along an elongateddirection of said stripe along a first crystal orientation of saidsemiconductor substrate for improving a device performance of saidMOSFET power transistor and a trench termination end surface at terminalends of said elongated stripe having a significantly less areas thansaid sidewalls along said elongated direction along a second crystalorientation of said semiconductor substrate different from said firstcrystal orientation; and forming a single dielectric layer covering saidsidewalls and said termination end surface wherein said dielectric layerhaving different formation growth rates along said first crystalorientation and said second crystal orientation wherein said end surfacehaving significant less areas than said sidewalls for reducing effectscaused by said different formation growth rate along said second crystalorientation.
 39. The method of claim 38 further comprising a step of:forming said sidewall along a (110) crystal orientation and saidtermination end surface along a (100) crystal orientation for improvinga device performance because of sidewalls formed along said (110)crystal orientation and for reducing device performance differencesarising from said end surface formed along said (100) crystalorientation having significant less areas than said sidewalls.
 40. Themethod of claim 38 further comprising a step of: manufacturing saidMOSFET power transistor as a P-channel MOSFET power transistor andforming said sidewalls along a (110) crystal orientation of saidsemiconductor substrate having a sidewall area significant greater thanan area of said end surface for enhancing a P-type carrier mobilitywhereby said P-channel MOSFET power device having a reducedon-resistance.
 41. The method of claim 38 further comprising a step of:forming said MOSFET power transistor as an N-channel MOSFET powertransistor and forming said sidewall along said elongated directionalong a (100) crystal orientation and said termination end surface alonga (110) crystal orientation wherein said end surface havingsignificantly less area than said sidewall.
 42. The method of claim 38further comprising a step of: manufacturing said MOSFET power transistoras a N-channel MOSFET power transistor and forming said trench with abottom surface formed along a (110) crystal orientation to form a singlethermally grown oxide layer thereon having a greater thickness than asingle thermally grown oxide layer on said sidewall to reduce agate-to-drain capacitance.